Celebrating its twenty-fifth anniversary in 2016, Cyient is an acknowledged leader in engineering design services, design-led manufacturing, networks and operations, data transformation, and analytics. We collaborate with our clients to help them achieve more and together shape a better future. We call it Designing Tomorrow Together.
Our industry focus includes aerospace, defense, rail transportation, off-highway & industrial, power generation, mining, oil & gas, communications, utilities, geospatial, semiconductor and medical technology. We align closely with the business needs, goals, culture, and core values of our clients. This reflects in the deep, long-standing relationships we have developed and sustained with some of the leading names in these industries.
JOB DESCRIPTION SUMMARY
- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level
- Develop IP level/SoC level test plans based on the design/architectural specs.
- Coverage Analysis and Coding
- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues
- Define and develop block/full chip level verification environment and its components
- 6+ years of experience in ASIC Verification and Methodologies
- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies
- Good understanding of RTL concepts
- Good understanding of AHB/AXI protocol
- Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage
- Knowledge of Perl/TCL is Must
- Good communication skill
6 to 9 Years.
Experience in ASIC Verification and Methodologies
Define and develop block/full chip level verification environment and its components
Develop IP level/SoC level verification plans and test plans based on the design/architectural specs.
Expertise in System Verilog, SV-OVM/SV-UVM Methodologies
Coverage Analysis and Coding
Good understanding of RTL concepts
Good understanding of AHB/AXI protocol
Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage
Good communication skill
Good to have
Knowledge in Processor based systems verification will be an advantage
Knowledge of Perl/TCL
Exposure to Cadence, Synopsys and Mentor Graphics tools