Due to the current health crisis related to COVID-19 and the escalating visa/travel restrictions in place, we're currently unable to extend offers to anyone who cannot work from Bengaluru due to lockdown visa/travel restrictions, or other restrictive measures until further notice. Consequently, we will be prioritizing candidates who can start in this location by set date as expected. We're keeping the situation under review and would adjust our position should the restrictive measures be removed later on.
Bachelor's degree in Electrical Engineering or equivalent practical experience.
2 years of experience.
Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
Experience in high performance synthesis, PnR and sign-off optimizations. Experience in sign-off convergence, including STA, electrical checks and physical verification.
Experience in computer architecture.
Knowledge of Verilog/SystemVerilog.
Understanding of circuit design, device physics and deep submicron technology.
Effective skills with scripting languages such as Python, Tcl, and/or Perl.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a Physical Design and Implementation Engineer, you will develop high performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will work with Architects and Logic Designers to drive architectural feasibility studies, develop timing and area design goals and exploring RTL/design tradeoffs for physical design closure. You'll also work with Verification and Software teams to understand and implement the design requirements for clocking management.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Develop all aspects of ASIC RTL2GDS implementation for high PPA designs.
Manage block and full-chip level physical implementation and QoR (timing, area).
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.