VLSI Design Lead Design Engineer for 5G 3GPP NR Systems
abc consultants
Bengaluru, Karnataka
Job Description
Develop a differentiated system by understanding the hardware architecture of a system and optimize its design.
Develop an optimal system by understanding and designing a system s software architecture and subsystems.
Develop an optimal system which integrates service and application by applying system software to system hardware.

Job Description

Design and development of digital HW modules (on FPGA/ASIC using Verilog) for 3GPP 5G NR wireless modem technologies. Responsible for designing, modeling, verifying and integrating the digital sub-systems implemented on the state of art FPGAs/ASICs.

Areas of interest are (one of them): either (a) or (b) and (c) is must

Type 1:
RTL design for digital signal processing logic design (in Verilog/VHDL), like filter, fft, matrix operations, control, LTE/3G layer 1 channels like PUCCH, PUSCH, PDCCH, PDSCH etc. on FPGAs

Type 2:
FPGA based CPRi/eCPRi/Ethernet IP handling with XRAN design understanding (best to have)/RTL design for SERDES interfaces on FPGA systems

c) Extremely good hands on digital design.

Project deliverables includes models/algorithms of digital modem sub-systems on FPGA/ASICs; these models are to be

Bit-accurate matches to the corresponding MATLB/C/other implementation,
Meeting very strict timing requirements and
Are to be used for link-level performance characterization and field trials with RF. - Apply critical problem solving skills of complex modem subsystems including PHY, RF, and lower stack implementation.

Additional Job Description

Has a wide range of experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways
Works on complex issues where analyzing situations or data requires an in-depth evaluation of variables. Exercises judgement in selecting methods, techniques and evaluation criteria to obtain results. Determines methods and procedures on new assignments and coordinates other's tasks
May manage a group such as coordinating activities regarding costs, methods and staffing
Typically requires at least 8 years of related experience and a Bachelor's degree; or 6 years and a Master's degree; or a PhD with 3 years
Key Skills
RTL
VLSI
FPGA/ASICs
PUCCH
PUSCH
PDCCH
PDSCH
FPGA
RTL design
SERDES interfaces
Education
B.Tech/B.E.