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  • The job involves leading a team of engineers involved in Developing Testbench environment in System Verilog, Development of chip level & /or block level test-bench using SystemVerilog/Verilog/Syste mc/C++ on Verification IPs/ in SoC environment. Good to have exposure to AXI buses, and involved in SoCVerification verification Should be able to mentor the new joiners, guide the team to achieve timely ...

  • high verification coverage coverage points, code coverage - Good working knowledge in SV/UVM. - IP/SoC verification experience. - Knowledge in AHB/AXI/APB protocols. - Experiance in PCIE,USB, DDR2 is desirable Domain: Subsystems/SOC DDR3/DDR4 USB2.0/3.0 PCIe gen3/4 Graphics Image Processing Audio Display I2C SPI GPIO Security (AEE, Crypto etc) CPU (Intel, ARM) SD eMMC uART SATA SDIO MIPI-CSI MIPI-DSI

  • high verification coverage coverage points, code coverage - Good working knowledge in SV/UVM. - IP/SoC verification experience. - Knowledge in AHB/AXI/APB protocols. - Experiance in PCIE,USB, DDR2 is desirable Domain: Subsystems/SOC DDR3/DDR4 USB2.0/3.0 PCIe gen3/4 Graphics Image Processing Audio Display I2C SPI GPIO Security (AEE, Crypto etc) CPU (Intel, ARM) SD eMMC uART SATA SDIO MIPI-CSI MIPI-DSI

  • high verification coverage coverage points, code coverage - Good working knowledge in SV/UVM. - IP/SoC verification experience. - Knowledge in AHB/AXI/APB protocols. - Experiance in PCIE,USB, DDR2 is desirable Domain: Subsystems/SOC DDR3/DDR4 USB2.0/3.0 PCIe gen3/4 Graphics Image Processing Audio Display I2C SPI GPIO Security (AEE, Crypto etc) CPU (Intel, ARM) SD eMMC uART SATA SDIO MIPI-CSI MIPI-DSI

  • high verification coverage coverage points, code coverage - Good working knowledge in SV/UVM. - IP/SoC verification experience. - Knowledge in AHB/AXI/APB protocols. - Experiance in PCIE,USB, DDR2 is desirable Domain: Subsystems/SOC DDR3/DDR4 USB2.0/3.0 PCIe gen3/4 Graphics Image Processing Audio Display I2C SPI GPIO Security (AEE, Crypto etc) CPU (Intel, ARM) SD eMMC uART SATA SDIO MIPI-CSI MIPI-DSI

  • 1. Experience on verification environment like SOC/ ASIC / FPGA / IP Verification 2. Verification environment setup 3. Verification experience using: Verilog, System Verilog 4. Work experience in methodologies like OVM, UVM 5. Verification experience at the chip level 6. Basic Analog and RF

  • 1. Experience on verification environment like SOC/ ASIC / FPGA / IP Verification 2. Verification environment setup 3. Verification experience using: Verilog, System Verilog 4. Work experience in methodologies like OVM, UVM 5. Verification experience at the chip level 6. Basic Analog and RF

  • 1. Experience on verification environment like SOC/ ASIC / FPGA / IP Verification 2. Verification environment setup 3. Verification experience using: Verilog, System Verilog 4. Work experience in methodologies like OVM, UVM 5. Verification experience at the chip level 6. Basic Analog and RF

  • 1. Experience on verification environment like SOC/ ASIC / FPGA / IP Verification 2. Verification environment setup 3. Verification experience using: Verilog, System Verilog 4. Work experience in methodologies like OVM, UVM 5. Verification experience at the chip level 6. Basic Analog and RF

  • 1. Experience on verification environment like SOC/ ASIC / FPGA / IP Verification 2. Verification environment setup 3. Verification experience using: Verilog, System Verilog 4. Work experience in methodologies like OVM, UVM 5. Verification experience at the chip level 6. Basic Analog and RF

  • test and coverage plan and Verification environment. UVM/OVM/VMM, System Verilog is must. Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage ...

  • test and coverage plan and Verification environment. UVM/OVM/VMM, System Verilog is must. Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage ...

  • test and coverage plan and Verification environment. UVM/OVM/VMM, System Verilog is must. Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage ...

  • test and coverage plan and Verification environment. UVM/OVM/VMM, System Verilog is must. Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage ...

  • test and coverage plan and Verification environment. UVM/OVM/VMM, System Verilog is must. Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage ...

  • test and coverage plan and Verification environment. UVM/OVM/VMM, System Verilog is must. Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage ...

  • - SOC/IP Verification PCIe/SATA/USB , HighSpeed BUS - Develop and Review Test Plan based on design specification - Develop constrained-Random verification environment for complex DUT - Implement coverage matrix using cover point and assertion - Hands on experience with SystemVerilog/UVM

  • - SOC/IP Verification PCIe/SATA/USB , HighSpeed BUS - Develop and Review Test Plan based on design specification - Develop constrained-Random verification environment for complex DUT - Implement coverage matrix using cover point and assertion - Hands on experience with SystemVerilog/UVM

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