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  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • and modify SOC-level, and sub-system level test benches. - Develop new tests to improve functional/code coverage. - Running and debugging Top level regression. - Formal equivalence checking - Gate level/Power simulations - Help support post-silicon debug. - Timely and high quality execution per

  • Independent In-charge of the FPGA Design Blocks Experienced with any one of the Interfaces such as : - PCIe 2.0, SATA, Fiber Channel, 1G/10G BASE - MII/RMII/GMII/RGMII/SGMII/XAUI,RXAUI, - SDI- SD/HD/3G , Display Port , USB, JESD204B, SRIO, - MIPI, DDR/LPDDR/DDR2/DDR3, QDR memories Hands on Experience on Design and Debugging. Should had worked on projects based on FPGAs, SOC SOC , Hi Speed Interfaces

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

  • projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently

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