Total Experience: 3 to 11 years Jobel Role : ASIC/VLSI Verification Engineer Work location : Noida. Job Description: Experience on Verilog, System Verilog languages: Experience on OVM/UVM/VMM methodologies Experience on Microprocessor core verification Test bench development, Test case
design leads in delivering high quality standard/custom cell layouts in a timely manner. In-depth proficiency in sub-micron technologies 28nm, 20soc, 16nm, 14nm, 10nm. Good understanding of the standard cell library architecture, ASIC design flow and semi-custom design flows. Hands-on layout experience
Architecture, design and RTL coding of Block level and chip level RTL development Worked on complex data path designs and/ IP development Participate in DFT insertion and integration of SoCs.DFT audits and sign off Participate in synthesis and timing analysis , Required knowledge and skills:VLSI
At least 3 years of experience in VLSI layout design or ASIC design automation, CAD tool development and tool integration The Candidate will be responsible for Automation of standard cell and custom cell design flow. Automation of standard cell and custom cell library release procedures ...
Skills/Experience: - • •Principal Engineer to lead Physical Design activities on the next high complexity ASIC/Advanced technology node. •Candidate should be familiar with all phases of ASIC design from synthesized gates to GDS. •This includes floorplanning, power estimation, DFT, place
Job Description This internship position is for a person with an aptitude and interest to work and be part of SoC, ASIC development. Responsibilities may include synthesis, automatic place and route, floor planning, timing analysis, integration and design convergence for leading edge Fabric HFI