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5966 jobs found for Fpga Engineer Manager

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  • Education and Work Experience Requirements: B.Tech/M.Tech - EE/ECE/CS with 12-16 years experience Experience in Embedded C++ software development Experience in automotive In-Vehicle Infotainment development preferably Navigation Experience in managing Technical projects/programs

  • Education and Work Experience Requirements: B.Tech/M.Tech - EE/ECE/CS with 12-16 years experience Experience in Embedded C++ software development Experience in automotive In-Vehicle Infotainment development preferably Navigation Experience in managing Technical projects/programs

  • and collaboration. Supervise the Team of around 48 people (Utilities & Maintenance &EIA ) and facilitate their development and guide for better performance 20. Preparing yearly energy report showing plan Vs actual on site energy improvement PROJECT MANAGEMENT: a. Budget preparation for next year projects in both Other Requirements: a. Supporting Maintenance Supervisor and Utilities Supervisor during major ...

  • Should have Valve/Pump Industry Exp Monitoring and arrangement of drawings and required specification. Availability of approved drawings on UWS Managing VC and PDM support Preparation of project plan with complete work package, scope, timeline etc. Complete realization of product development as per the plan and its monitoring within the department and with other team members. Create technical ...

  • Should have Valve/Pump Industry Exp Monitoring and arrangement of drawings and required specification. Availability of approved drawings on UWS Managing VC and PDM support Preparation of project plan with complete work package, scope, timeline etc. Complete realization of product development as per the plan and its monitoring within the department and with other team members. Create technical ...

  • Should have Valve/Pump Industry Exp Monitoring and arrangement of drawings and required specification. Availability of approved drawings on UWS Managing VC and PDM support Preparation of project plan with complete work package, scope, timeline etc. Complete realization of product development as per the plan and its monitoring within the department and with other team members. Create technical ...

  • Should have Valve/Pump Industry Exp Monitoring and arrangement of drawings and required specification. Availability of approved drawings on UWS Managing VC and PDM support Preparation of project plan with complete work package, scope, timeline etc. Complete realization of product development as per the plan and its monitoring within the department and with other team members. Create technical ...

  • and escalate issues and risks tim ely. o Leads the delivery, implementation, and improvement of all applicable processes and methodologies. o Provides on-going support to business teams on strategic technology platform, quality assurance and issue resolution. o Directly manages and mentors engineering

  • and delivery of projects from conceptualization, visualization to technology mapping and final execution of projects Implementation and execution of project management practices Managing Project scope and change requests (CR) Interact with the client to create technology specifications from business Reqirements - Well versed with Agile project method techniques. Seek and participate in personal growth ...

  • 3-8 years of automotive CAE experience * Preprocessor - Hypermesh - Hands on with proficiency * Posprocessor - MetaPost/Hyperworks - Proficient * Solver - Nastran/Optistruct - Good Knowledge * Good NVH fundamentals * Proficient in PT integration. * OEM experience * Automotive powertrain architecture - Good knowledge * Morphing and optimization Tools - Exposure

  • Digital / Mixed Signal Design Experience for consumer/industrial/medical markets. ARM / Processor based Design Experience - TI, NXP, Freescale, Qualcomm, Renesas, Xilinx, Altera FPGA. Experience in High Level and High Speed Design Audio and Video Design Experience Cameras(USB/MIPI/Parallel), Customer communication and front ending for technical aspects. Resources required for EMS company. Product qualification ...

  • Digital / Mixed Signal Design Experience for consumer/industrial/medical markets. ARM / Processor based Design Experience - TI, NXP, Freescale, Qualcomm, Renesas, Xilinx, Altera FPGA. Experience in High Level and High Speed Design Audio and Video Design Experience Cameras(USB/MIPI/Parallel), Customer communication and front ending for technical aspects. Resources required for EMS company. Product qualification ...

  • Digital / Mixed Signal Design Experience for consumer/industrial/medical markets. ARM / Processor based Design Experience - TI, NXP, Freescale, Qualcomm, Renesas, Xilinx, Altera FPGA. Experience in High Level and High Speed Design Audio and Video Design Experience Cameras(USB/MIPI/Parallel), Customer communication and front ending for technical aspects. Resources required for EMS company. Product qualification ...

  • Digital / Mixed Signal Design Experience for consumer/industrial/medical markets. ARM / Processor based Design Experience - TI, NXP, Freescale, Qualcomm, Renesas, Xilinx, Altera FPGA. Experience in High Level and High Speed Design Audio and Video Design Experience Cameras(USB/MIPI/Parallel), Customer communication and front ending for technical aspects. Resources required for EMS company. Product qualification ...

  • Responsible for and own all aspects of physical design and physical verification effort at a block level, STA, FPGA, DFT & Analog Layout Verticals,Netlist to GDSII at block level for multiple tape-outs, * Timing closure with Crosstalk & OCV (Advanc

  • Responsible for and own all aspects of physical design and physical verification effort at a block level, STA, FPGA, DFT & Analog Layout Verticals,Netlist to GDSII at block level for multiple tape-outs, * Timing closure with Crosstalk & OCV (Advanc

  • Responsible for and own all aspects of physical design and physical verification effort at a block level, STA, FPGA, DFT & Analog Layout Verticals,Netlist to GDSII at block level for multiple tape-outs, * Timing closure with Crosstalk & OCV (Advanc

  • Responsible for and own all aspects of physical design and physical verification effort at a block level, STA, FPGA, DFT & Analog Layout Verticals,Netlist to GDSII at block level for multiple tape-outs, * Timing closure with Crosstalk & OCV (Advanc

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