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  • Total of 5- 6 years of experience with a minimum of 3 years in Automation Experience working with automating IOS/ Android mobile applications using Appium on the Perfecto Platform Experience in automating electron based applications using Java and Selenium Strong hands on experience in delivering end to end test automation solutions Hands on Experience in using Perfecto Mobile platform for ...

  • Total of 5- 6 years of experience with a minimum of 3 years in Automation Experience working with automating IOS/ Android mobile applications using Appium on the Perfecto Platform Experience in automating electron based applications using Java and Selenium Strong hands on experience in delivering end to end test automation solutions Hands on Experience in using Perfecto Mobile platform for ...

  • DV: Location : Bangalore HM: Bhomesh Sharma Recruiter: Taufiq JD: Develop new test vectors in Programmable System - on - Chip (PSoC) according to block and product specifications Create and integrate test vectors for simulation and debugging Follow on design methodology , checklist and design review documentations Delivery on - time with good quality Test vector flow automation for productivity At least 5 years ...

  • RTL: Location : Bangalore HM : Bhomesh Sharma Recruiter : Taufiq JD: experience in RTL based digital design (VHDL / Verilog) In Depth knowledge on Digital Signal Processing sub - blocks like Digital filters , FFT , IFFT , Digital Echo Cancellers would be mandatory. Domain Knowledge on Ethernet physical layer is an added advantage. Candidate having experience in SoC , Module integration would also be an added advantage ...

  • DFT Position: Hiring Manager : Bhomesh Recruiter : Sai Susrutha V EXP - 5 - 8 yrs NO. Head count : 2 Location Bangalore JD - DFT Skills : a. Fundamentals of SCAN stuck - at and at - speed techniques. Expertise in handling Mentor Graphics EDT logic. b. Knowledge on On chip clock controller (OCC). Pattern generation with Mentor Graphics TestKompress Tool. c. Good knowledge in BSCAN operations. d. Good Knowledge in MBIST ...

  • DFT Position: Hiring Manager : Bhomesh Recruiter : Sai Susrutha V EXP - 5 - 8 yrs NO. Head count : 2 Location Bangalore JD - DFT Skills : a. Fundamentals of SCAN stuck - at and at - speed techniques. Expertise in handling Mentor Graphics EDT logic. b. Knowledge on On chip clock controller (OCC). Pattern generation with Mentor Graphics TestKompress Tool. c. Good knowledge in BSCAN operations. d. Good Knowledge in MBIST ...

  • Responsible for floor planning , place and route , Clock Tree Synthesis , Clock Distribution , extraction , Timing analysis , Power and Signal Integrity Analysis and Physical Verification of Low power and high frequency designs. Technology: 7nm / 14nm / 16nm / 28nm

  • STA/ Synthesis Design Engineer / Lead Engineer/ Engineering Manage Location: Noida, India Client : Synopsys / STM HM : Varnit Jain Recruiter : Joseph JD: Experience : 3 to 7 years Technology : 7nm/ 14nm/ 16nm/ 28nm Tools : Design Compiler/ Genus/ PrimeTime/ Tempus Job Description: Exposure to Synthesis, static timing analysis (STA) and timing sign- off experience with: o Low power design techniques and checks o Logical ...

  • DV: Location : Bangalore HM: Bhomesh Sharma Recruiter: Taufiq JD: Develop new test vectors in Programmable System - on - Chip (PSoC) according to block and product specifications Create and integrate test vectors for simulation and debugging Follow on design methodology , checklist and design review documentations Delivery on - time with good quality Test vector flow automation for productivity At least 5 years ...

  • Physical Design Engineer / Lead Engineer/ Engineering Manager Location : Noida , India Client : Synopsys / STM HM : Varnit Jain Recruiter : Joseph JD: Experience : 3 to 7 years Technology 7nm/ 14nm/ 16nm/ 28nm Tools : ICC/ ICC2 / Innovus Job Description: Responsible for floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing analysis, Power and Signal Integrity Analysis and Physical ...

  • 4 Years experiance Responsible for floor planning , place and route , Clock Tree Synthesis , Clock Distribution , extraction , Timing analysis , Power and Signal Integrity Analysis and Physical Verification of Low power and high frequency designs ...

  • 4 Years experiance Responsible for floor planning , place and route , Clock Tree Synthesis , Clock Distribution , extraction , Timing analysis , Power and Signal Integrity Analysis and Physical Verification of Low power and high frequency designs ...

  • to innovate, to integrate new and better technologies and methods into our products. Exposure and experience to a broad array of technical disciplines, including networking. This person needs to be able to flex between packaging and QA/testing assignments. Application Packaging, Operating Systems, Admin

  • technical issues to Development for queries received from clients. Raise tickets to internal teams or third party Development team to fix the bugs/ do enhancements related to either feed or Product ...

  • and confidential Ability to recognize technical limitations and surface issues to appropriate parties Ability to anticipate, identify and solve critical problems Ability to work independently in absence of daily supervision, exercising sound judgment and initiative Ability to learn out of mistakes The above

  • and confidential Ability to recognize technical limitations and surface issues to appropriate parties Ability to anticipate, identify and solve critical problems Ability to work independently in absence of daily supervision, exercising sound judgment and initiative Ability to learn out of mistakes The above

  • and confidential Ability to recognize technical limitations and surface issues to appropriate parties Ability to anticipate, identify and solve critical problems Ability to work independently in absence of daily supervision, exercising sound judgment and initiative Ability to learn out of mistakes The above

  • for customer needs. This invol ves resolving post-sales technical customer Service Requests via electronic and phone means, as well as, technical questions regarding the use of and trouble sh ooting of Solaris Operating System product. Solaris administrator/expert (SME), who has minimum 6 years of relevant

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