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Senior Verification Engineer/lead

Pune, Maharashtra

Connect pro management consultant

Job Description

The incumbent will be responsible for the Verification and Validation of Digital IP & sub systems. This includes understanding the specifications, proposing an exhaustive & regressive verification environment

Detailed Responsibilities description:

Responsibilities include

Complete Design Verification of digital modules/IPs developed for highly complex SoCs/ASICs to address automotive application.

SoC Verification (specs. understanding and micro-architecture definition, RTL coding,) targeted towards Automotive applications


Must have skills:

Sound Verilog HDL RTL knowledge and working knowhow of RTL simulations

Plan, develop, debug Testbench and Verification Suite at IP module and SoC level.

RTL (Verilog/VHDL/system verilog) coding.

Sound knowhow of System Verilog for testbench with exposure to verification methodologies like UVM, VMM etc.

Assertion based verification or working experience on formal verification (IFV, Jasper)

Technical troubleshooting, debugging and demonstrated problem solving skills

RTL code quality and rule checks using spyglass will be desirable.

Exposure to gate level simulation and debugging skills.

Experience on any of the defect management tools

Good to have skills:

Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

Solutions orientation; Quality driven; Execution minded; Customer focused

Qualification & Experience

BTech/BE/MTech/ME/MSc in Electronics

5 to 8 years Experience

Company Description

Consultancy Firm.

Additional Information

Last updated:
Job type:
Full time
Position type:
Minimum experience:
Between five and ten years
Compulsory Education
Jobs in Engineering / R&D
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