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Senior RTL Engineers

Rajkot, Gujarat


Job Description

Hands-on in Verilog/VHDL
Hands on in Linting, Clock Domain Crossing (CDC) checks, equivalence checks
Experience in Digital module micro-architecture and design
Experience in basic RTL simulation
Good knowledge of Synthesis, STA and DFT aware design
Hands-on in Perl/Unix scripting
Hands on in SoC level RTL integration
Excellent analytical, and problem solving skills
Self-motivated, assertive, positive attitude, excellent communication skills and ability to excel in a team environment.
Be able to work with teams at remote locations with different time zone.
Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the project's success
Roles & Responsibilities

Perform Microarchitecture and detailed block design from system requirements/specifications
Perform RTL coding, Lint checks, CDC checks, SDC creation, equivalency checking, STA result review, RTL/gate level simulations debugging
Creating timing constraint file
Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals
Technical interaction with customers and support team
Guiding a team of junior engineers

Company Description

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Additional Information

Last updated:
Job type:
Full time
Position type:
Minimum experience:
Between three and five years
Compulsory Education
Jobs in Engineering / R&D
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