Senior Verification Engineers / Leads
Our client is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to designSoC. HQ in, California, with multiple development and services centers in India, Canada , Malaysia and Germany
Digital Verification team is working on IP verification and SoC verification projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently at client/s/Customer work location.
3-10 years of verification experience
Hands-on work experience in SoC & IP Level Verification or Verification IP Development
Experience in developing Verification Environment for IP/SoC using SystemVerilog and UVM
Hands-on experience in developing Test Plans, Coverage plan
Experience in development of Test cases/Scenarios, assertions, cover-points, etc.
Work experience in protocols such as PCIe, Ethernet, USB, MIPI, DDR, etc.
Hands-on experience in Gate Level Simulation
Experience in Industry Standard Simulation tools
Good Communication Skill & Learning Attitude.
Roles & Responsibilities
Work on SoC/Sub-system/IP verification projects for our customers
Define and develop Verification environment using SV/UVM or other methodology
Define Test plan, develop test cases and verify the design
Achieve code and functional coverage as desired
Run gate level simulation
Work independently owning the technical deliverables
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