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Senior Design Engineer - RTL /logic Design

Bangalore, Karnataka

UST Global

Job Description

Exp in design implementation using Verilog/ VHDL
Architecture and specification development starting from high level architecture to micro architecture.
Expertize in RTL coding, standalone testbench coding, updating existing RTL code for designs optimized for power, performance, area and timing.
Design Tools/Flows/Methodology (Linting, CDC, SpyglassLP)
Synthesis DC
Expertize on industry standard simulators including NCSim/ VCS/ Modelsim and expertize industry standard debug tools.
Understanding of low power micro architecture techniques

REQ 1:
Experience: 4yrs-9 years.
Job Location: Bangalore & Noida
Strong logic design background with ability to prototype RTL design into FPGA using Verilog
Engineer must have the capability to modify large SoC designs to fit into the multiple FPGA.
FPGA tool flows (include Xilinx/Altera/Lattice)
Knowledge in Verilog/VHDL, FPGA synthesis, place and route, timing analysis and Validation
Experience in Synopsys HAPS Prototyping solution and Protocompiler is added advantage
Experience with bring-up and debug of FPGA based designs.

Company Description

it is cmm level 5 company

Additional Information

Last updated:
25/10/2017
Job type:
Full time
Position type:
Permanent
Vacancies:
1
Minimum experience:
Between three and five years
Education:
Compulsory Education
Category:
Jobs in Engineering / R&D
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