Location: Hyderabad/ Bangalore
Experience: 3-12 yrs
Notice Period - 30 days (Negotiable)
Profile: Senior Analog Layout Engineer
Roles and Responsibility
Analog layout requirement for SERDES IP being done in 7nm. Scope involves scratch layout design.
This position requires 3+ Industry experience and has worked on 7nm/10nm analog/custom layout.
Good understanding of analog concepts along with experience in layout design of complex analog circuits is required.
Should have worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IOs or Standard cells, integration and taking the block from specification to release.
Responsibilities will include floor planning, DRC/LVS verification and fix, Reliability Analysis and fix, implementation.
Should have good debugging skills.
Hands-on experience with Cadence tools for custom layout.
Qualification: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics
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