Experience: 3yrs to 8yrs
Responsible to execute development and verification activities individually/in team with/without guidance.
Will be involved in developing Testbench for the Block / Cluster, Testcases, Tesplans and Functional and Code coverage.
Experience in developing test and coverage plan and Verification environment.
UVM/OVM/VMM, System Verilog is must.
Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage.
it is cmm level 5 company