Experience : 3 yrs to 10yrs
Qualification: Bachelor/ Master s Degree in Electronic/ Electrical Engineering with Major in VLSI/ Microelectronics
In depth knowledge/ experience of System Verilog UVM.
Experience & good understanding of ASIC/ FPGA pre- silicon verification concept i.e. focus vs full/ constraint random testing, coverage based verification, testbench, it vs full chip testing.
Experience in coverage points coding, SV test writing & debug testbench.
Explored to EDA simulation tools i.e. Modelsim/ Questasim/ VCS/ NCsim or debug tools i.e. Verdi/ Debussy.
it is cmm level 5 company