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Design & Verification Engineer

Hubli, Karnataka

UST Global

Job Description

IP /Soc Verification
Experience: 3yrs to 8yrs
Responsible to execute development and verification activities individually/in team with/without guidance.
Will be involved in developing Testbench for the Block / Cluster, Testcases, Tesplans and Functional and Code coverage.
Experience in developing test and coverage plan and Verification environment.
UVM/OVM/VMM, System Verilog is must.
Knowledge of industry standard protocols like Ethernet, PCIe, MIPI. will be added advantage.

Company Description

it is cmm level 5 company

Additional Information

Last updated:
Job type:
Full time
Position type:
Minimum experience:
Between three and five years
Compulsory Education
Jobs in Engineering / R&D
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