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Design Verification Engineer

Delhi, Delhi-NCR

UST Global

Job Description

- SOC/IP Verification PCIe/SATA/USB , HighSpeed BUS
- Develop and Review Test Plan based on design specification
- Develop constrained-Random verification environment for complex DUT
- Implement coverage matrix using cover point and assertion
- Hands on experience with SystemVerilog/UVM

Company Description

it is cmm level 5 company

Additional Information

Last updated:
17/07/2018
Job type:
Full time
Position type:
Permanent
Vacancies:
1
Minimum experience:
Between three and five years
Education:
Compulsory Education
Category:
Jobs in Engineering / R&D
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