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Asic/soc/ip Verification Engineers

Vijayawada, Andhra Pradesh

UST Global

Job Description

- IP Verification /SoC verification/USB/GPIO
- Develop and Review Test Plan based on design specification
- Develop constrained-Random verification environment for complex DUT
- Implement coverage matrix using cover point and assertion
- Create and debug tests for UT
- Resolve bugs with remote designers
- Part of Serdes Technology Group in Programmable Platform Group
- Hands on experience with System Verilog/UVM
- Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering
- Strong understanding of verification process from test plan to coverage completion
- Strong communication and Analytical skills
- Understanding of HDL (Verilog, VHDL, SV)

Company Description

it is cmm level 5 company

Additional Information

Last updated:
Job type:
Full time
Position type:
Minimum experience:
Between three and five years
Compulsory Education
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