M/s HOMEOCARE INTERNATIONAL P LTD

Hyderabad, Andhra Pradesh

Company details

Industry:
Healthcare
Number of workers:
500
Website:

Company Description

Homeocare International, commenced by a team of dedicated and committed doctors strive to provide exceptional quality medical care, in a patient –friendly and completely comfortable ambience that is reassuring and comforting.A highly qualified panel of Doctors comprising of experienced Homeopaths dedicated to Global Homeopathy are ever willing to help you with your ailments, using world-class techniques, latest advances, hi-tech technology and sophisticated software for the diagnosis and treatment of the diseases without any side effects.

M/s HOMEOCARE INTERNATIONAL P LTD

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job postings

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Experience Level:4 to 9years Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT teams to define design ...

  • Education: Graduate Degree in Electrical/Electronics Engg. (post Graduate is a plus) Experience/Skills: - 4-14 years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes) - Experience with CSI/DSI debug - RTL Design and ...

  • Education: Graduate Degree in Electrical/Electronics Engg. (post Graduate is a plus) Experience/Skills: - 4-14 years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes) - Experience with CSI/DSI debug - RTL Design and ...

  • Education: Graduate Degree in Electrical/Electronics Engg. (post Graduate is a plus) Experience/Skills: - 4-14 years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes) - Experience with CSI/DSI debug - RTL Design and ...

  • Education: Graduate Degree in Electrical/Electronics Engg. (post Graduate is a plus) Experience/Skills: - 4-14 years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes) - Experience with CSI/DSI debug - RTL Design and ...

  • Education: Graduate Degree in Electrical/Electronics Engg. (post Graduate is a plus) Experience/Skills: - 4-14 years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes) - Experience with CSI/DSI debug - RTL Design and ...

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