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796 jobs found for Engineering / R&d in Karnataka

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  • The successful candidate will be working in Intel's Corporate CAD organization to develop and deploy an end-to -end RTL to GDS Tools, Flows and methods (TFM) for Intel's SOC products. Our TFM integrates internal & external CAD engines for logic Verification, simulation, synthesis, formal equivalency, static and structure checkers and signoff tools . We develop innovative solutions that provide added ...

  • Job Description: Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing ...

  • Intel's Big Core India team is chartered to design and develop the core for next generation microprocessors . During his/her internship, candidate will do hands-on design work on next generation microprocessor project. Candidate's responsibilities may include design and verification of advanced microprocessor circuits, timing analysis, functional equivalence verification, power optimization ...

  • Job Description: Responsibilities may be quite diverse of an exempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Graduate Intern

  • The candidate will be responsible for the Voltage regulators, switching regulators, Buck converter, low power circuit design, and reliable analog and digital circuits for various areas of Linear Drop out Voltage regulator. The various task involves, circuit design, validation, mixed signal validation, and reliability validation. The job also involves to work with stakeholders such as mask designer for ...

  • Job Opportunity/Description: In this position, you will be responsible for being a member of a team of verification engineers to verify and deliver world class intellectual property to various business groups within Intel. Tasks include writing test plans for functional coverage, defining the architecture of test benches, developing verification methodologies and mentoring verification engineers in the ...

  • JJob Opportunity/Description: In this position, you will be responsible for being a member of a team of verification engineers to verify and deliver world class intellectual property to various business groups within Intel. Tasks include writing test plans for functional coverage, defining the architecture of test benches, developing verification methodologies and mentoring verification engineers in ...

  • Job Description: Your responsibilities will include but not be limited to: The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of IO PHY. The various task involves, circuit design, validation, mixed signal validation, and reliability validation. The job also involves to work with stakeholders such as mask designer for circuit ...

  • Job Description: Your responsibilities will include but not be limited to: The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of IO PHY. The various task involves, circuit design, validation, mixed signal validation, and reliability validation. The job also involves to work with stakeholders such as mask designer for circuit ...

  • Job Description: The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of IO PHY. The various task involves, circuit design, validation, mixed signal validation, and reliability validation. The job also involves to work with stakeholders such as mask designer for circuit implementation, and logic designer to design the analog/digital ...

  • Microarchitecture Research Labs located in Bangalore, India is seeking proficient Graduate Research Interns. Main responsibilities will include power/area/performance driven architecture and microarchitecture development and optimization of CPU, GPU or SoC interconnect and platform architecture. Complementary activities include prototype development: logic design and RTL development followed by ...

  • candidate should able to repair,install or design equipment,tools and products. . candidate should have two wheeler. qualification: b.tech(B.E) experience: 0-2 years salary: 10-12k

  • Job Description: Develops software for Test Automation as the primary job function; This position is for a Software Engineer (SE) for the ISecG Consumer Partner Automation team. The SE will be responsible for design, development and maintenance of test automation scripts, web interface, reporting services and various other services managed by the partner automation team. Candidate should have excellent ...

  • Job Description: Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgment on a variety of ...

  • Online risk does not only come from malicious code. Intel Security Group's Cloud Security team is building the capabilities to understand and manage the risk of access and data transactions that take place on Web-Based applications and services. We are looking for a team of experts to perform manual (and potentially automated) inspection of Cloud Applications to evaluate the risk and security ...

  • Job Description: -- In this position, candidates responsibilities include understand the SoC interfaces with packaging, Full-Chip power delivery and Analog blocks integration at Full-Chip level. -- Create diefiles , bumpmap creations based on floorplan -- Facilitate IO planning to meet constraints from floor-plan & package -- Full chip clock tree build, deriving latency & skew numbers, understand clock typologies ...

  • Job Description: In this position, candidate will be responsible for Back-End implementation of complex blocks with couple of million instances -- This includes resolving issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, multi-power domain complexities, Place & Route, clock tre synthesis complexities like balancing the clocks between multiple clocks, LVS & DRC cleanup, timing closure ...

  • Job Description: -- In this position, candidate will be responsible to lead the design team and be interface with Front-end team to resolve the RTL related issues. -- This includes, drive the team to resolve issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, Place & Route, clock generation, LVS & DRC cleanup, static timing, Electrical Rule Fixes and Quality fixes. -- Candidate will also be ...

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