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261 jobs found for Engineering / R&d in Karnataka

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  • POSITION DETAILS: Designation: Presales & Design Engineer - AV Industry: Audio Video Functional Area: Presales, AV Solution/ BOQ Designing, Estimation Salary: As per Industry Standards Exp: 3 – 5yrs Location: Bangalore DESIRED CANDIDATE PROFILE: 1 Coordinating with internal sales teams to understand the client requirements. 2 Presales Support - Need to visit clients place along with sales person to understand about ...

  • POSITION DETAILS: Designation: Project Engineer Industry: Audio Video Functional Area: Project Management, On Site/Office Support, Project Installations Salary: As per Industry Standards Exp: 1 – 3yrs Location: Bangalore DESIRED CANDIDATE PROFILE: 1 The ability to explain design ideas and plans clearly and decision-making ability, Interpret clients' requirements and Identify engineering problems and ensure ...

  • Good academic record and graduated (B.E/B.Tech/MS/PhD) from a reputed institution 10-15 years of IT experience with the following skills B.S. in computer science (or similar) or equivalent experience , 10+ years of system administration experience with Solaris/Linux, 8+ years of Unix, Linux systems experience in a 24x7 environment, 6+ years of experience with analyzing business requirements and designing ...

  • Primary Responsibilities: Provide sustaining engineering support Create OEM electrical component symbols using Zuken E3.series Create symbols & footprints needed for PCB design using Cadence OrCAD & Allegro Update database part status and other library management activities. Mandatory Skills required to performing the job: Should have good electrical component knowledge Experience in library parts ...

  • Should be a mechanical engineer with 1 to 3 yr experience either in MPM link or Process planning. Should have knowledge of heavy sheet metal fabrication and welding. Create MBOM, work instructions and process plans (Labor routings) using MPM link software. Continual learning: Maintains up to date proficiency with the use of PTC softwares (eg: Creo Parametric, windchill, MPM link, etc) Initiative: Actively seeks ...

  • Should have experience in CATIA software to design the gear. Should have good knowledge in Pro e software. Should have experience in Gear industry. Should have experience in Pumps or compressors or turbines industry ...

  • Responsible for understanding the product validation requirements from customer specification Experience in coordinating tasks across multiple geographical locations, providing the validation report to customer,cross functional competencis Any B.E/B.tech/M.tech with experience 7 - 12 Years into Validation/any discipline in embedded product development are Preffered ...

  • Description: Experience in one or more of the following tasks: Synthesis, Formal Verification, Power Analysis, Static Timing Analysis Experience in post-layout timing analysis and generating ECOs Good understanding of timing constraints at block-level Experience in formal verification RTL-to-netlist and netlist-to-netlist Worked in technology nodes 45nm and below Knowledge of low-power aware ...

  • Understanding the feature test plans and test cases documents. Add/Update test cases documents, execute test cases (manually and using automation) and develop automation scripts. SkillSet: Good understanding of Android platform and its components and experience in testing Android systems. Knowledge of VOIP, PoS & networking concepts would be an advantage Experience in using JIRA, GIT Experience in using MS ...

  • Will be responsible for Designing and Implementing DFT techniques. (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression.. Implementing, integrating and verifying memory BIST and boundary scan . Test vector (Stuck-at ...

  • Desired Skills & Experience: Must possess Good hands on experience in the Hardmacro through P&R from Netlist to GDS including timing closure and Physical verification (Proficient in Synopsys ICC, Magma Talus or Cadence FE tool set.). Design experience in all aspects of physical design. Proficient in Synopsys ICC, Magma Talus or Cadence FE tool set. Experience with Mentor Olympus tool is a Plus ...

  • Description: Experience in one or more of the following DFT techniques: Test-plan creation, Memory-BIST, Scan, Compression, At-speed Scan, Test-clocking, Boundary-Scan, Analog Testing, Logic-BIST, ATPG, Test-point insertion Experience in generation and simulations of the DFT vectors Very good understanding of complete SOC design and flows Able to complete the tasks independently and mentor junior engineers ...

  • Description: Experience in one or more of the following tasks: Synthesis, Formal Verification, Power Analysis, Static Timing Analysis Experience in post-layout timing analysis and generating ECOs Good understanding of timing constraints at block-level & top-level Experience in formal verification RTL-to-netlist and netlist-to-netlist Worked in technology nodes 45nm and below Knowledge of low-power aware ...

  • Description: Experience in one or more of the following tasks: Synthesis, Formal Verification, Power Analysis, Static Timing Analysis Experience in post-layout timing ECOs Good understanding of timing constraints at block-level Experience in formal verification RTL-to-netlist and netlist-to-netlist Worked in technology nodes 45nm and below Hands-on experience in one or more of the DFT tools: DC/RC, DC-T ...

  • Description: Experience in one or more of the following tasks: Synthesis, Formal Verification, Power Analysis, Static Timing Analysis Experience in post-layout timing analysis and generating ECOs Good understanding of timing constraints at block-level Experience in formal verification RTL-to-netlist and netlist-to-netlist Worked in technology nodes 45nm and below Knowledge of low-power aware ...

  • Description: Experience in one or more of the following tasks: Synthesis, Formal Verification, Power Analysis, Static Timing Analysis Experience in post-layout timing analysis and generating ECOs Good understanding of timing constraints at block-level & top-level Experience in formal verification RTL-to-netlist and netlist-to-netlist Worked in technology nodes 45nm and below Knowledge of low-power aware ...

  • Description: Experience in one or more of the following tasks: Synthesis, Formal Verification, Power Analysis, Static Timing Analysis Experience in post-layout timing ECOs Good understanding of timing constraints at block-level Experience in formal verification RTL-to-netlist and netlist-to-netlist Worked in technology nodes 45nm and below Hands-on experience in one or more of the DFT tools: DC/RC, DC-T ...

  • Description: Experience in one or more of the following DFT techniques: Test-plan creation, Memory-BIST, Scan, Compression, At-speed Scan, Test-clocking, Boundary-Scan, Analog Testing, Logic-BIST, ATPG, Test-point insertion Experience in generation and simulations of the DFT vectors Very good understanding of complete SOC design and flows Able to complete the tasks independently and mentor junior engineers ...

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