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  • Strong ethics and integrity. Knowledge in CE marking and FDA ISO 13485, documentation Strong technical/functional knowledge. 4 -8 years of experience in Medical Devices Engineering / BE / Biomedical/Electronics ECG, Patient monitors, Multipara monitors, defibrillators, Xray/C-arm, Syringe Pumps, Infusion pumps Work location Bangalore Strong ethics and integrity. Knowledge in CE marking and FDA ISO 13485 ...

  • Technical Requirements : (in order of importance) Mandatory 5-8 years of overall verification experience Hands-on work experience in SoC Experience in verifying SOC peripherals using ARM C and ARM processors Good experience in C and Exposure to Assembly Good AXI/AHB bus knowledge and ARM based SOC/Testbench exposure. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Work ...

  • Technical Requirements : (in order of importance) Mandatory 3-5 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • Technical Requirements : (in order of importance) Mandatory 5-8 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • Software Developer to design Svasth device - a health management initiative. 1. SQL & ASP.NET WITH 2 TO 3 YEARS EXPERIENCE. ASSIGNMENT IS TO DEVELOP GST SOFTWARE 2. PHP AND MYSQL – for Developing E-commerce Software, 2 TO 3 YEARS EXPERIENCE 3. ANDROID APPS & IOS APPS : around 2 years experience with experience in Developing APPS ...

  • Job Description: Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgment on a variety of ...

  • Job Description: -- In this position, candidate will be responsible to lead the design team and be interface with Front-end team to resolve the RTL related issues. -- This includes, drive the team to resolve issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, Place & Route, clock generation, LVS & DRC cleanup, static timing, Electrical Rule Fixes and Quality fixes. -- Candidate will also be ...

  • Job Description: In this position, candidate will be responsible for Back-End implementation of complex blocks with couple of million instances -- This includes resolving issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, multi-power domain complexities, Place & Route, clock tre synthesis complexities like balancing the clocks between multiple clocks, LVS & DRC cleanup, timing closure ...

  • In this position, you will be responsible for all aspects of STA & timing closure activities of Intel's SoCs in lower technology nodes. Your tasks will include but not limited to: - Design & Architecture understanding, Interaction with FE/DFT/Verification teams - Clocking, Constraints development, ACIO Timing, Understanding on synchronous & asynchronous paths, Clock domain crossing issues - Understanding and ...

  • Job Description: Deep understanding of Quality standards like GS5000, ISO 9000 and models like CMMI. Authors detailed software quality requirements to meet Intel quality standards. Works with product development teams throughout the product development life cycle to ensure software quality requirements and goals are established and met. Trains the team on quality engineering practices. Drives effective ...

  • Candidate will be responsible for owning performance evaluations for system on a chip products from early projections through post silicon measurements. They will have a strong background in performance and performance tool flows including architectural explorations, evaluation for design alternatives, performance and power projections and pre/post-Silicon performance validation. This role will ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. The candidate will be part of a group that focuses on developing flows, methodology and automation for various aspects of DFT. This includes DFT logic insertion, construction and validation. The role ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. The candidate will be part of a group that focuses on developing flows, methodology and automation for various aspects of DFT. This includes DFT logic insertion, construction and validation. The role ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. Candidates should be well versed with industry standard DFT techniques such as scan/ATPG, memory Built-in-Self-Test (MBIST), Test Access Port (TAP), boundary scan, I/O testing, etc. The role also involves ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. The candidate will be part of a group that focuses on developing flows, methodology and automation for various aspects of DFT. This includes DFT logic insertion, construction and validation. The role ...

  • Understand the product/module requirement and come up with required test plans and scripts for automated testing. Interaction with design teams and working towards resolving bugs, ensuring that the product meets the quality and usability expectations Reviewing product documentation and providing feedback Setting up and maintaining a QA test bed and process for the Network Security appliances ...

  • The Security Research team are responsible for working alongside Support and Sales organizations to drive anti-malware incident response and provide quality resolution to customers across the globe. The role requires the ability to coordinate with other teams throughout the Intel Security Group and will occasionally require direct interaction with customers. Successful candidates will be analyzing ...

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