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54 jobs found for Vlsi Design

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  • development, design processes and methodology Experience in coordinating on multiple programs and people. Must have exceptional drive and demonstrated ability working with cross-functional teams Excellent verbal and written communication skills with good presentation skills Must be willing to manage multiple

  • Candidate should have 3+ years of experience in SOC/IP verification. Candidate should be strong in the design(Verilog/VHDL) and verification language(System verilog). Prior expertise with OVM/UVM based testbench development. Candidate should be able to work on testplan development, functional SOC/IP verification Verilog/VHDL System verilog OVM/UVM Expertise in any one verification protocol like PCIe, USB ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC Hands-on experience in floor planning, placement optimizations, CTS and routing. Exposure in physical implementation of timing/functional ECO’s Good knowledge of VLSI process and device characteristics TCL, perl scripting

  • which includes VHDL,Verilog, C/System-C/System-Verilog/Specman, communication systems & standards (DSL, WLAN, Ethernet), processor IP cores (MIPS, ARC),high-speed interfaces (USB, PCIe, DDR, xGMII) and ASIC design flow(RTL to GDS) would be desirableInterestedcandidates contact to the below number

  • Job ID: JR0013323 Job Category: Engineering Primary Location: Bangalore, KA IN Other Locations: Job Type: College Grad Big Core Design Engineer Job Description Develops and supports digital circuit design for cell libraries. Performs custom digital circuit design and simulation ...

  • Verification of layouts for design and architecture rules* Understanding and implementation of DFM and ESD guidelines* Understanding of RC delay, electro migration, self-heating and coupling capacitance* Ability to recognize failure prone layout structures and produce robust layouts* Equivalence verification

  • and ExperienceB.Tech + 2-3 yrs experience or M.Tech in VLSI. CMOS basics, analog design basics required. Experience with Cadence Virtuoso Custom tool suite, ICV/Calibre verification is a plus. Good communication skills essential. Inside this Business Group As the world's largest chip manufacturer, Intel strives

  • and methodologies of choice in the associated domains on leading edge microprocessors in Intel India. You will be expected to work with key stakeholders in design, central CAD, other projects on similar technologies and local CAD teams. You will also be expected to define and drive next generation tools

  • and associated IP's in Intel India. You will be expected to work with key stakeholders in design, central CAD, other projects on similar technologies and local CAD teams. You will also be expected to participate in the development of next generation tools and methodologies in physical design world closely

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