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71 jobs found for Design Engineer Vlsi Verification India

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  • * Anantha Cybertech Pvt Ltd is established in the year of 2003 specialized in IT, Non IT, ITES. Ours is an MNC company with ISO CERTIFIED. * Anantha Cyber Tech Pvt Limited, India is a auxiliary company of Anantha Limited, UK which is one of the fastest growing "Global IT Service Provider ...

  • Emulation / silicon validation experience. Knowledge of Perl, UNIX shell. Good communications skills, both verbal and writing. SoC Expertise/Domain Knowledge ARM processor knowledge and integration ARM AXI,AHB/APB protocol knowledge ARM AXI peripheral integration and verification Industry

  • is responsible for the successful development and delivery of the complete programs, co-ordination of the program deliveries and timelines with customer, and management of inter-dependencies, including oversight of any risks and issues Education & Experience: Bachelors or Masters degree in Engineering and/or

  • regressions and coverage analysis Working with SoC team, for reviews and issues Qualifications The applicant should have Bachelor/Master's degree in Electrical Electronics or Computer System or related Engineering or equivalent with 5-7 years of pre-silicon verification experience. Sound understanding

  • cross-team/cross-site (US/India/Europe) product issues Requirements Bachelor’s Degree or Master Degree (MCA) in computers/information systems required. 4 to 6 years of relevant experience. Must have experience in testing one or more of the following technologies: Web/HTTP/GUI Should have experience in installing, configuring and deploying applications on Weblogic and JBoss Must have experience with ...

  • engineers to verify and deliver world class intellectual property IP to various business groups within Intel. Tasks include writing test plans for functional coverage, defining the architecture of test benches, developing verification methodologies and mentoring verification engineers in the team ...

  • inclusive of module and top-level chip level SoC designs, Test bench architecture and development, State of the art verification methodologies and flow, independent creation of test benches/test cases, verify module and top-level designs, Gate level simulations and understanding of Emulation and FPGA

  • which includes VHDL,Verilog, C/System-C/System-Verilog/Specman, communication systems & standards (DSL, WLAN, Ethernet), processor IP cores (MIPS, ARC),high-speed interfaces (USB, PCIe, DDR, xGMII) and ASIC design flow(RTL to GDS) would be desirableInterestedcandidates contact to the below number

  • engineers to verify and deliver world class intellectual property IP to various business groups within Intel. Tasks include writing test plans for functional coverage, defining the architecture of test benches, developing verification methodologies and mentoring verification engineers in the team ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • Design, development and verification of state of the art Analog and Mixed Signal IPs (mainly PLLs and blocks of PLL like VCO, PFD, Charge-Pump, Current Reference, LDO, Frequency Dividers etc.). Knowledge of Circuit Theory, Control Systems, Good understanding of CMOS and VLSI technologies (device physics and layout effects and sub-micron effects). Proficient in usage of all EDA tools used in analog mixed signal ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

  • P&R of digital design blocks from Netlist to GDS, Signoff and Verification for the same. Block Implementation: Backend Implementation of various blocks i.e. floor planning, placement, Clock tree synthesis & routing. EDA tools: Encounter/Innovus, ICCompiler1/2, Primetime, Calibre, Virtuoso * Knowledge of CMOS & VLSI design fundamentals * Digital design basics * Working knowledge of Unix and ability to do Shell/Tcl ...

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