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  • The Oracle Hyperion Solution Architects will be responsible for driving the design and implementation of Hyperion Planning / Hyperion Financial Management solutions. This position will provide an expert consultative edge for expediting the ROI, and maximize the effectiveness, of their business performance management and business intelligence solutions. In this role you will act as a business solution or ...

  • (IPSPL) incorporated in The Year 2004, with intent to deliver integrated solution for Recruitment, HR Management/processing and HR outsourcing for IT and non IT companies. Today, our pro-customer approach and our endeavor to deliver perfect solution for our client’s requirements in the most efficient and economical way, we have created a niche for Ourselves as end–to-end HR outsourcing solution provider ...

  • Able to understand schematics board file Understanding of key concepts in following domains - Graphics, Audio, Networking, Camera /Imaging, BIOS/Firmware, will be relevant for this role Knowledge of IP protocols, debugging connectivity modules WLAN, WWAN, GPS, NFC,BT Familiarity with power equipment (NI DAQ/multimeters) board design Experience, software debug tools such as Windbg, ITP/Lauterbach, Xperf, GPUView etc ...

  • A minimum of 3 years in Android development is required. Knowledge in developing software in Java and experience in Android. Experience in object oriented Inheritance and multi-threaded programming is also a requirement. Worked on Wifi/WLAN/Bluetooth/NFC with Android & Java will be an advantage. Experience in Agile methodologies is a definite plus ...

  • 5+ years work experience in embedded software and/or driver development . Extremely strong knowledge of C/C++ programming. Solid understanding of ARM assembly language and low level ARM debugging . Strong understanding of low level software/hardware interface design and debugging . Experience with display technologies and standards such as HDMI/DSI/LVDS/eDP. Working knowledge with display bridge chips that ...

  • Leading a team of 2 to 5 members. Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation. Block level implementation from netlist to GDS. Handling timing closure of high frequency blocks. Handling blocks of high instance counts 1M instance and above. Expertise in signoff closure- Timing with SI and OCV, Power, IR and Physical ...

  • Candidate must have transistor level layout drawing experience for full-custom or memory compilers with hands-on experience in drawing sense-amp and other critical memory circuitry. Have worked one or more of 180nm to 28nm process technologies and must have good understanding of complex DRC rules and should be able to interpret the rules from the DRM or calibre deck. Must have good understanding on ...

  • Design and development of Analog/Mixed signal hard macros in cutting edge process technologies 22nm, 28nm, 45nm and 65nm Experience in complete Analog design cycle transistor level design, SPICE circuit simulation, parasitic extraction, post layout simulations and layouts. Strong domain knowledge and experience in analog/mixed signal/custom-digital circuit design in one or more areas 1. High Speed ...

  • Leading a team of 2 to 5 members. Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation. Block level implementation from netlist to GDS. Handling timing closure of high frequency blocks. Handling blocks of high instance counts 1M instance and above. Expertise in signoff closure- Timing with SI and OCV, Power, IR and Physical ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques Should have ...

  • Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc. Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches, Building environment. Knowledge of Functional coverage using HVL language features or assertions a plus. Should be ARM based ...

  • Design and develop WLAN software for a variety of enterprise-class mobile computers including support for voice over WLAN. Develop Windows/Linux Device Driver in Kernel Mode and User Mode Engineer will be responsible for feature development, performance enhancements, and the successful integration of WLAN stacks into enterprise mobile computers. Engineer will work with a diverse team including ...

  • JOB DESCRIPTION Candidate must have transistor level layout drawing experience for full-custom or memory compilers with hands-on experience in drawing sense-amp and other critical memory circuitry. Have worked one or more of 180nm to 28nm process technologies and must have good understanding of complex DRC rules and should be able to interpret the rules from the DRM or calibre deck. Must have good ...

  • Candidate to have hands-on experience and knowledge of SRAM compiler or custom memory characterization. Candidate to have understanding of memory architectures, critical paths in design, mis-match margin simulations and characterization flows and tools for process nodes 28nm and 45nm. Candidate must have good understanding in generating timing views, validation of data and QA process for release ...

  • Design and development of Analog/Mixed signal hard macros in cutting edge process technologies 22nm, 28nm, 45nm and 65nm Experience in complete Analog design cycle transistor level design, SPICE circuit simulation, parasitic extraction, post layout simulations and layouts. Strong domain knowledge and experience in analog/mixed signal/custom-digital circuit design in one or more areas 1. High Speed ...

  • Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation Block level implementation from netlist to GDS Handling timing closure of high frequency blocks Handling blocks of high instance counts 1M instance and above Expertise in signoff closure Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level ...

  • Hands on expertise in Linux Kernel and Drivers Testing on Linux/Android based platforms (Mobile, Automotive) Should have worked on Linux Platform Testing tools like LTP, Yocto Test framework, etc Should have good understanding of Linux Debug FS, Procfs/Sysfs for different SoC components, clock, regulators level validation Hands on with shell, perl, python Test Scripts development Should have minimum 3 years ...

  • To work independently on layout design Responsible for timely and quality execution of layout design Design and Develop layouts for given schematics, physical verification checks and actively participate in layout review. Mentoring new team members Key responsibilities: Experience level: 3- 10 Years To design and develop layouts for Standard cells and Custom digital cells. Layout design of GPIOs, DDR ...

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