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  • Software Developer to design Svasth device - a health management initiative. 1. SQL & ASP.NET WITH 2 TO 3 YEARS EXPERIENCE. ASSIGNMENT IS TO DEVELOP GST SOFTWARE 2. PHP AND MYSQL – for Developing E-commerce Software, 2 TO 3 YEARS EXPERIENCE 3. ANDROID APPS & IOS APPS : around 2 years experience with experience in Developing APPS ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Block/Top level RTL synthesis Logical Synthesis including scan insertion and constraint development. Block level and top level timing closure Automation of flows using perl/tcl Working on STA concepts like derates, margins , sta corner

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers

  • the next wave of growth in SDG's design engineering team in Bangalore. This leader will drive all SDG product development and innovation activities at the site, reporting to the VP/GM of SDG. Responsibilities include: Managing all engineering projects, initiatives, and processes in alignment with SDG

  • Job Description: In this position, candidate will be responsible for Back-End implementation of complex blocks with couple of million instances -- This includes resolving issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, multi-power domain complexities, Place & Route, clock tre synthesis complexities like balancing the clocks between multiple clocks, LVS & DRC cleanup, timing closure ...

  • Job Description: -- In this position, candidate will be responsible to lead the design team and be interface with Front-end team to resolve the RTL related issues. -- This includes, drive the team to resolve issues in RTL2GDS flow like, Logic synthesis, FEV, Block level floor-planning, Place & Route, clock generation, LVS & DRC cleanup, static timing, Electrical Rule Fixes and Quality fixes. -- Candidate will also be ...

  • In this position, you will be responsible for all aspects of STA & timing closure activities of Intel's SoCs in lower technology nodes. Your tasks will include but not limited to: - Design & Architecture understanding, Interaction with FE/DFT/Verification teams - Clocking, Constraints development, ACIO Timing, Understanding on synchronous & asynchronous paths, Clock domain crossing issues - Understanding and ...

  • Job Description: Deep understanding of Quality standards like GS5000, ISO 9000 and models like CMMI. Authors detailed software quality requirements to meet Intel quality standards. Works with product development teams throughout the product development life cycle to ensure software quality requirements and goals are established and met. Trains the team on quality engineering practices. Drives effective ...

  • Candidate will be responsible for owning performance evaluations for system on a chip products from early projections through post silicon measurements. They will have a strong background in performance and performance tool flows including architectural explorations, evaluation for design alternatives, performance and power projections and pre/post-Silicon performance validation. This role will ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. The candidate will be part of a group that focuses on developing flows, methodology and automation for various aspects of DFT. This includes DFT logic insertion, construction and validation. The role ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. The candidate will be part of a group that focuses on developing flows, methodology and automation for various aspects of DFT. This includes DFT logic insertion, construction and validation. The role ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. The candidate will be part of a group that focuses on developing flows, methodology and automation for various aspects of DFT. This includes DFT logic insertion, construction and validation. The role ...

  • Job Description: This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. Candidates should be well versed with industry standard DFT techniques such as scan/ATPG, memory Built-in-Self-Test (MBIST), Test Access Port (TAP), boundary scan, I/O testing, etc. The role also involves ...

  • Understand the product/module requirement and come up with required test plans and scripts for automated testing. Interaction with design teams and working towards resolving bugs, ensuring that the product meets the quality and usability expectations Reviewing product documentation and providing feedback Setting up and maintaining a QA test bed and process for the Network Security appliances ...

  • The Security Research team are responsible for working alongside Support and Sales organizations to drive anti-malware incident response and provide quality resolution to customers across the globe. The role requires the ability to coordinate with other teams throughout the Intel Security Group and will occasionally require direct interaction with customers. Successful candidates will be analyzing ...

  • Job Description: Principal Engineers at Intel are active technical leaders inside and outside the company. Activities include participation in major industry and academic conferences, voting membership in international standards committees, generation of patents and technical papers. Note - This job code can only be assigned if an employee has participated in an official Technical Leadership Program (TLp ...

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