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  • is for a software design intern in Intel Labs team (Currently Six months - extendable to One year) in Bangalore. Below are the preferred qualifications: - Background in mathematics and computer science. - Good knowledge of C/C++. - Basic knowledge of robotic algorithms (such as, localization, path planner ...

  • is for an intern in Intel Labs team in Bangalore. Currently for Six months can be extended for one year. Below are the preferred qualifications: - Background in electronic and electrical engineering. - Knowledge of control systems (open-loop/closed-loop, PID implementation experience). - Basic experience

  • is for a circuit design intern in Intel Labs team in Bangalore. Below are the preferred qualifications: - Basic knowledge of VLSI devices and sub-micron characteristics. - Knowledge of VLSI circuit design fundamentals (CMOS, high-speed digital circuits, low-power digital circuits; concept of timing analysis

  • Microarchitecture Research Labs located in Bangalore, India is seeking proficient Graduate Research Interns. Main responsibilities will include power/area/performance driven architecture and microarchitecture development and optimization of CPU, GPU or SoC interconnect and platform architecture ...

  • Intel Labs have recently established the Microarchitecture Research Lab (MRL) in Bangalore, India. MRL is a world-class research lab that excels at novel product development through fundamental architecture research and transformative design exploration techniques. The India Lab specifically ...

  • Team Lead 3G/HSPA System Engineering Description: We are expanding our 3G modem activities in Bangalore and looking for a team lead for a 3G-HSPA modem system engineering team. Our solutions are used in world-class tablets, smartphones, feature-phones, and wireless modules. This job opening

  • Intel's Microarchitecture Research Lab located in Bangalore, India is seeking proficient Graduate Research Interns. We are in the early advanced research phase of the 2020+ generation of CPU/GPU products on Intel's roadmap. As research intern, you will develop and use software to model, analyze

  • the next wave of growth in SDG's design engineering team in Bangalore. This leader will drive all SDG product development and innovation activities at the site, reporting to the VP/GM of SDG. Responsibilities include: Managing all engineering projects, initiatives, and processes in alignment with SDG

  • Job Description: Develop pre-Silicon functional validation tests to verify system will meet design requirements. Create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. VLSI design and verification experienced with ASIC design flow, Verification of digital ...

  • Job Description: Develop pre-Silicon functional validation tests to verify system will meet design requirements. Create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. VLSI design and verification experienced with ASIC design flow, Verification of digital ...

  • Job Description: Develop pre-Silicon functional validation tests to verify system will meet design requirements. Create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. VLSI design and verification experienced with ASIC design flow, Verification of digital ...

  • Job Description: Develop pre-Silicon functional validation tests to verify system will meet design requirements. Create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. VLSI design and verification experienced with ASIC design flow, Verification of digital ...

  • Job Description: Participates in the development of Architecture and Micro-architecture specifications for the IP Logic components. Performs logic design, Register Transfer Level (RTL) coding, and simulations, designs functional units, and sub-systems for inclusion in full chip designs. Domain experience in communication technologies, architecture model development, System-C Models, Simulations for signal ...

  • Job Description: Participates in the development of Architecture and Micro-architecture specifications for the IP Logic components. Performs logic design, Register Transfer Level (RTL) coding, and simulations, designs functional units, and sub-systems for inclusion in full chip designs. Domain experience in communication technologies, architecture model development, System-C Models, Simulations for signal ...

  • Job Description: Participates in the development of Architecture and Micro-architecture specifications for the IP Logic components. Performs logic design, Register Transfer Level (RTL) coding, and simulations, designs functional units, and sub-systems for inclusion in full chip designs. Domain experience in communication technologies, architecture model development, System-C Models, Simulations for signal ...

  • Job Description: Participates in the development of Architecture and Micro-architecture specifications for the IP Logic components. Performs logic design, Register Transfer Level (RTL) coding, and simulations, designs functional units, and sub-systems for inclusion in full chip designs. Domain experience in communication technologies, architecture model development, System-C Models, Simulations for signal ...

  • Job Description: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs ...

  • In this position, the candidate is expected to lead/work with a team of engineers to design the building blocks (soft IPs) for Intel’s next generation chips (including SOCs) for the different market segments. The candidate will be responsible for all reviews which include microarch reviews, code reviews, tool reviews. Also candidate will interface with SOC teams in closing all issues related to the IP ...

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