Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • 1. Good knowledge in spice modeling of PWM controllers, OpAmps, Drivers, etc 2. Tool knowledge of Pspice(OrCad), LTspice, etc 3. Strong basics of network analysis, Control Theory 4. Good in written and spoken communication 5. Go-Getter attitude

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • 1. Basic idea of circuits/electronics. Need not be good in it 2. Good in coding, programming 3. If good in Object Oriented Programming, PHP, Perl, spice language, it will be added advantage 4. Interest in Automations/programming 5. Good in written and spoken communication - Direct interaction with customer will be needed in the project 6. Go-Getter attitude 7. Online tool development, based on PHP, Java, Perl, 8. The ...

  • 1. Good knowledge in spice modeling of PWM controllers, OpAmps, Drivers, etc 2. Tool knowledge of Pspice(OrCad), LTspice, etc 3. Strong basics of network analysis, Control Theory 4. Good in written and spoken communication 5. Go-Getter attitude

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • " Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence SoC Encounter EDA Tool flow is required. At least 2 Full Chip T/O experience for 8 years experienced engineers

  • Block/Top level RTL synthesis Logical Synthesis including scan insertion and constraint development. Block level and top level timing closure Automation of flows using perl/tcl Working on STA concepts like derates,margins , sta corner Experience on Block/Top level RTL synthesis for a minimum of 3-4 projects with a good understanding of clocks in the design and related relationships Good understanding ...

  • Block/Top level RTL synthesis Logical Synthesis including scan insertion and constraint development. Block level and top level timing closure Automation of flows using perl/tcl Working on STA concepts like derates,margins , sta corner Experience on Block/Top level RTL synthesis for a minimum of 3-4 projects with a good understanding of clocks in the design and related relationships Good understanding ...

  • Job Responsibility - 4+ years of hands-on experience in RF/analog layout - Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, DAC, ADC, PLL, LDO etc. - Full Understanding of IC fabrication and reliability issues - Full familiarity with Cadence Virtuoso and Mentor Graphics Calibre tools - Work experience in 65nm and below technology nodes - Outstanding written and verbal ...

  • Job Responsibility - 4+ years of hands-on experience in RF/analog layout - Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, DAC, ADC, PLL, LDO etc. - Full Understanding of IC fabrication and reliability issues - Full familiarity with Cadence Virtuoso and Mentor Graphics Calibre tools - Work experience in 65nm and below technology nodes - Outstanding written and verbal ...

  • Job Responsibility - 4+ years of hands-on experience in RF/analog layout - Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, DAC, ADC, PLL, LDO etc. - Full Understanding of IC fabrication and reliability issues - Full familiarity with Cadence Virtuoso and Mentor Graphics Calibre tools - Work experience in 65nm and below technology nodes - Outstanding written and verbal ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

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