Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • Technical Requirements: Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM ...

  • Testplan creation Program implementation Hardware debugging and characterization on bench. Board design and simulation Hands on experience on tester platforms Must is Advantest or Verigy 93K Should have preferably worked on atleast one more platform like Eagle or VLCT Worked on testplan creation, program implementation and debug and characterization Experience of working with different product lines ...

  • Technical Requirements: Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM ...

  • Good Knowledge about IO Layout, should have work experience on 55nm and below .Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS. .Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation in Layout Design. .Sound knowledge of IO blocks like Design of the General purpose IO, Transmitter /Receiver Blocks, Level Shifters. Exposure to DDR IOs, XTAL IOs an ...

  • Prior Experience : 3+ Years Hands on Experience in Interface circuit design Circuit design of General purpose IO, Overvoltage tolerant & Drive cells, LVDS TX & RX, or any other differential signalling like USB 1.1, 2.0 transceiver, Sound knowledge on layout related issues in IOs Know how on ESD & latch up is a plus Experience/Knowledge on De-emphasis, or Receive side equalization is a plus Must have worked on ...

  • Looking for Standard Cell Characterization with 3 years experience. Schematic design, and Characterization of standard cells ...

  • Responsible for execution for SoC from spec to silicon . Acts as project leader with ability to contribute hands on if needed . Leads parallel teams for project development . Have a deep understanding on overall architectures as well as product related issues . Acts as single point of contact for customer as project manager Prior experience in managing SOC design team or working as Architect in SOC Design

  • Technical Requirement : o Prior Experience : 2-5 yrs o Design For Test experience, Scan insertion, ATPG (Test Pattern Generation) o Awareness of MemBIST flow o Familiarity with ATE, automatic test equipment o EDA Tools Synopsys, Mentor Graphics (Flextest/fastscan), Atrenta, etc., Good to have o Scripting knowledge on perl. SKILL Job description: o Understanding the overall design, preparing a test plan, doing scan ...

  • o Hands on experience on tester platforms. Must is Advantest/Verigy 93K. Should have preferably worked on atleast one more platform like Eagle or VLCT. o Worked on testplan creation, program implementation and debug and characterization. o Experience of working with different product lines. o Experience of characterization on bench. o Experience in hardware debug while performing the characterization ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • " Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence SoC Encounter EDA Tool flow is required. At least 2 Full Chip T/O experience for 8 years experienced engineers

  • Technical Requirements : (in order of importance) Mandatory - 3 to 6 years of overall verification experience and with at least 2.5 years of SV experience - Hands-on work experience in ASIC, SoC or IP Level Verification - Hands-on experience in building Test Plans, Verification Environments, Test cases/Scenarios - Hands-on in System Verilog (SV) and OVM / UVM based methodologies - Work experience in DDR Memories ...

  • Candidate will be working on Analog & Mixed Signal Layout & Design. Shortlisted candidates will receive mail notification containing drive date, location and selection procedure (written test, Group Discussion and interviews) Students who are 2015 passed out batch-- BE (E&C,E&E,Instrumentation Tech) and also for MTech (VLSI Design & Embedded Systems, MTech- VLSI Design & Testing, MTech- Digital Electronics ...

  • Development of the standard cell library from scratch and support of existing libraries enabling the ICF technology offerings to customers. Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR ...

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