Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence Synopsys ICC flow is required. At least 2 Full Chip Tapeout experience

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence Synopsys ICC flow is required. At least 2 Full Chip Tapeout experience

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence Synopsys ICC flow is required. At least 2 Full Chip Tapeout experience

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • Drive revenue within key accounts within the territory. Identify, prospect, and qualify new opportunities to grow revenue. Work closely with marketing and take advantage of their programs to maximize new opportunities, develop existing opportunities, and solidify customer relationships. Manage existing accounts for satisfaction, return on their investment, growth, and renewal. Manage complex sales cycle ...

  • (Part A or Part B may be pre-dominant in the person, but both parts are essential) Part A: SW design Priority of languages: 1. Perl, SKILL 2. TCL, Python 3. C, C++ Needs to be aware of best practices, complex SW development, not just pure automation. Should be able to create professional SW using design paradigms, data flow diagrams, class diagrams, implementation plan, and deliver code in the most efficient manner ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • 1. Very good analytical skills required 2. Understanding of design of EDA tools and/or CAD flows, must have been part of at least one such development. 3. Good programming (C, C++)/scripting (PERL, TCL, Python) knowledge and experience. 4. Understanding of SW engineering (SDLC). SW development expertise in OOD, programming, data structures, algorithm is a bonus ...

  • (Part A or Part B may be pre-dominant in the person, but both parts are essential) Part A: SW design Priority of languages: 1. Perl, SKILL 2. TCL, Python 3. C, C++ Needs to be aware of best practices, complex SW development, not just pure automation. Should be able to create professional SW using design paradigms, data flow diagrams, class diagrams, implementation plan, and deliver code in the most efficient manner ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

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