Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence Synopsys ICC flow is required. At least 2 Full Chip Tapeout experience

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • * Understand firmware and digital design engineers needs in daily work. * Recognize potential for optimization and develop tools to realize that potential jointly with the engineers. Generalize solution whenever useful. * Develop software tools to automate design steps of various complexity utilizing modern development techniques as model driven engineering/design, metamodeling, code generation * Contribute to ...

  • * Understand firmware and digital design engineers needs in daily work. * Recognize potential for optimization and develop tools to realize that potential jointly with the engineers. Generalize solution whenever useful. * Develop software tools to automate design steps of various complexity utilizing modern development techniques as model driven engineering/design, metamodeling, code generation * Contribute to ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers 4-7 years of overall verification experience Hands-on work experience in SoC & IP Level Verification, with predominant SoC ...

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers 4-7 years of overall verification experience Hands-on work experience in SoC & IP Level Verification, with predominant SoC ...

  • Block/Top level RTL synthesis Logical Synthesis including scan insertion and constraint development. Block level and top level timing closure Automation of flows using perl/tcl Working on STA concepts like derates, margins , sta corner

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