Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • - 3 to 6 years of overall verification experience and with at least 2.5 years of SV experience - Hands-on work experience in ASIC, SoC or IP Level Verification - Hands-on experience in building Test Plans, Verification Environments, Test cases/Scenarios - Hands-on in System Verilog (SV) and OVM / UVM based methodologies - Work experience in HDMI, MIPI, DDR Memories, Ethernet,PCIe & USB

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

  • Define and develop solution for physical design flow, SOC integration and PPA optimization of high performance and low power cores. Develop and qualify the methodology and implementation flow in advanced technologies like 10nm and below. Working closely with Foundries, process team, physical verification team and Physical design team. 8 - 12 years relevant in physical design flow, advanced design rules, DFM ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

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