Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • Technical Requirements : (in order of importance) Mandatory 5-8 years of overall verification experience Hands-on work experience in SoC Experience in verifying SOC peripherals using ARM C and ARM processors Good experience in C and Exposure to Assembly Good AXI/AHB bus knowledge and ARM based SOC/Testbench exposure. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Work ...

  • Technical Requirements : (in order of importance) Mandatory 3-5 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • Technical Requirements : (in order of importance) Mandatory 3-5 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence SoC Encounter EDA Tool flow is required. At least 2 Full Chip T/O experience for 8 years experienced engineers Desirable: Multi-million gate low-power ...

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence SoC Encounter EDA Tool flow is required. At least 2 Full Chip T/O experience for 8 years experienced engineers Desirable: Multi-million gate low-power ...

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence SoC Encounter EDA Tool flow is required. At least 2 Full Chip T/O experience for 8 years experienced engineers Desirable: Multi-million gate low-power ...

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence SoC Encounter EDA Tool flow is required. At least 2 Full Chip T/O experience for 8 years experienced engineers Desirable: Multi-million gate low-power ...

  • Technical Requirements : (in order of importance) Mandatory 5-8 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • Technical Requirements : (in order of importance) Mandatory 5-8 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • Technical Requirements : (in order of importance) Mandatory 5-8 years of overall verification experience Hands-on work experience in IP Level Verification Good AXI/AHB bus knowledge. Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios Hands-on in System Verilog (SV) and UVM based methodologies Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols Good to have Exposure to SoC ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

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