Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Hands-on work experience in Digital Physical Design (PD) at Full Chip Level, SoC or IP Level in technologies of 40 nm and below (28nm & 14nm) Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage Experience in Cadence Synopsys ICC flow is required. At least 2 Full Chip Tapeout experience

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers 4-7 years of overall verification experience Hands-on work experience in SoC & IP Level Verification, with predominant SoC ...

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers 4-7 years of overall verification experience Hands-on work experience in SoC & IP Level Verification, with predominant SoC ...

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers 4-7 years of overall verification experience Hands-on work experience in SoC & IP Level Verification, with predominant SoC ...

  • Defining verification plan Creating test bench environment following methodology Writing the simple to complex test cases/scenarios Define verification metrics and tracking for verification sign-off Customer interfacing for technical requirements Guiding the junior engineers 4-7 years of overall verification experience Hands-on work experience in SoC & IP Level Verification, with predominant SoC ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Experience of advanced custom circuit implementations. Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis, Marginality Analysis and Monte Carlo Simulations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Candidate must have significant exposure to ...

  • Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 65nm / 45nm / 28nm process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in ...

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