Sankalp Placement India P. Ltd

Mumbai, Maharashtra

Company details

Industry:
HR Consultancy
Number of workers:
49
Website:
http://www.sankalpplacement.com/

Company Description

Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.

Sankalp Placement India P. Ltd

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job postings

  • Needs to be aware of best practices, complex SW development, not just pure automation. Should be able to create professional SW using design paradigms, data flow diagrams, class diagrams, implementation plan, and deliver code in the most efficient manner. Relate to big picture, relate to top down requirement, with prior understanding of validation, integration, qualification. Ability to challenge current SW ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • Development of the standard cell library from scratch and support of existing libraries Circuit design: PPA tradeoff between different cell circuit architecture in realistic usage environment. Characterization and views generation of the libraries with several custom PVT corners. Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools. Maintain accurate and thorough ...

  • 1. Thorough in Analog basics 2. Experties in various IO design such as VML, CML and LVDS 3. Good knowledge in PLL, SERDES is required 4. Work experience on various serial IO standards such as DP/HDMI/ MIPI etc is a plus ...

  • - In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. - Analyze design and propose best compression technique. - Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. - Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Analog layout design of block level and chip level from schematics. Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

  • To work independently on Standard Cell layout design from schematics with minimal support from seniors. Hands on exp in Standard Cell Layout design. Good understanding of deep sub-micron and DFM issues and layout techniques. Should have basic work experience in CMOS process technologies - 28nm or 45nm, 65nm etc. Working knowledge of layout design and physical verification tools Cadence Virtuoso layout ...

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